Chips
Logic gates
Tiny circuits that make yes/no decisions. Each input is HIGH (1) or LOW (0), and the output follows a fixed rule: NOT flips it, AND needs all inputs high, OR needs any. Every processor is built from millions of them.
Pins
- Inputs
- : Must always be driven HIGH or LOW. Never leave an input floating.
- VCC / GND
- : Every logic chip needs power, plus a 100 nF decoupling capacitor next to it.
Logic comes as 14-pin chips with four gates each (the 74HC00 has four NAND gates), or as single-gate chips in tiny SOT-23 packages. Pin 14 is VCC and pin 7 is GND.
What to look for inside
- The simplest gate, a CMOS inverter (NOT), with its input switching between LOW and HIGH every 2 seconds.
- It is made of two MOSFETs: a P-channel to pull the output up and an N-channel to pull it down. The input drives both gates.
- Input LOW turns the top one on, so the output is HIGH. Input HIGH turns the bottom one on, so the output is LOW.
- Only one is ever on at a time, so a CMOS gate uses almost no power when it is not switching.
The numbers that matter
| Spec | Typical |
|---|---|
Family HC works from 2 to 6 V; HCT accepts 5 V TTL levels; LVC suits 3.3 V and below. | 74HC · 74HCT · 74LVC |
V_IH / V_IL The input voltages guaranteed to read HIGH and LOW. | ≈ 0.7 VCC / 0.3 VCC |
Propagation delay How long the output takes to react. | 2 ns to 20 ns |
Where you’ll use it
- Glue logic between chips: combining or inverting signals.
- Level shifting, buffering and clean-up of slow edges (Schmitt-trigger gates).
- Learning how computers work from the bottom up.
Common mistakes
- Unused inputs left floating. Tie them to VCC or GND.
- Mixing 5 V and 3.3 V logic without checking the input levels.
Lessons that use it
- Lesson 4.1: Pull-Up Resistors & Button Debounce Explained
- Lesson 4.2: Open-Drain vs Push-Pull Outputs (I2C Pull-Ups)
Go deeper
NOT, AND and OR in Boolean algebra.
CMOS power comes almost entirely from switching: capacitance × voltage² × frequency.